In certain aspects of the semiconductor packaging industry, semiconductor elements are bonded to bonding locations. For example, in conventional die attach (also known as die bonding) applications, a semiconductor die is bonded to a bonding location (e.g., a leadframe, another die in stacked die applications, a spacer, etc.). In advanced packaging applications, semiconductor elements (e.g., bare semiconductor die, packaged semiconductor die, etc.) are bonded to bonding locations of a substrate (e.g., a leadframe, a PCB, a carrier, a semiconductor wafer, a BGA substrate, etc.), with conductive structures (e.g., conductive bumps, contact pads, solder bumps, conductive pillars, copper pillars, etc.) providing electrical interconnection between the semiconductor element and the bonding location.
In many applications (e.g., thermocompression bonding of semiconductor elements including solder bumps, etc.) it is particularly desirable to have a significant level of parallelism between the bonding tool and respective portions of a support structure of the bonding machine. For example, there may be many interconnections between (1) the semiconductor element being bonded by the bonding tool, and (2) the substrate supported by the support structure. These interconnections may include solder or the like, and as such, it is particularly desirable that there be substantial parallelism between the contact portion of the bonding tool and respective portions of the support structure.
Thus, it would be desirable to provide improved systems for, and methods of, determining and adjusting the parallelism between elements of bonding machine.